Senior ASIC Physical Design Engineer – RTL to GDSII

Cisco Systems, Inc. in Yerevan invites a senior ASIC design engineer to lead RTL-to-GDSII physical implementation and signoff. You will collaborate with Front-End teams to translate architecture into optimal physical design, perform synthesis, floorplanning, placement, Clock Tree Synthesis, and routing while optimizing power, performance, and area. Join a global team delivering silicon excellence for the AI era.