Memory Layout Engineer

Cisco Systems, Inc. is seeking a senior-level physical design engineer for a hybrid role in Yerevan. You will implement SRAM layout and collaborate with international circuit teams to translate schematics into robust physical designs for critical silicon components. The role requires 5+ years in physical design, experience with Cadence or Synopsys, and familiarity with nodes from 22nm down to 2nm. You will ensure DRC cleanliness and support tapeouts in a fast-paced, global team environment.